FAULT INJECTION IN DYNAMIC PARTIAL RECONFIGURATION DESIGN BASED ON ESSENTIAL BITS
SEU or soft error is an unintended change to the state of a configuration memory bit caused by ionizing radiation which causes unacceptable changes in the design behavior. In this paper, a fault injection and mitigation system, based on Xilinx essential bits technology, for partial and non-partial reconfiguration sections of kintex-7 xc7k325t FPGA using Xilinx SEM IP core and the dual use of ICAP primitive is described. Dynamic Partial Reconfiguration Design (DPRD) or the Design Under Test (DUT) is implemented on FPGA. A MATLAB program is used to inject errors into configuration memory during runtime by controlling SEM IP core, which implemented into FPGA, via UART interface between PC running MATLAB and FPGA board. This system reduces the time required to inject errors into FPGA configuration memory by injecting errors into the essential bits of configuration memory. In addition, the system describes the dual use of ICAP primitive to perform both partial reconfiguration and soft error mitigation processes. Results show the dual use ICAP primitive is performed successfully, and the time needed to perform soft error injection and mitigation process using essential bits is reduced by 96% comparing with the traditional methods.
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